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tfaour 1b9226326a Fix hardware-verified bugs: EPD stack overflow and busy-wait spin
Two crashes found flashing to real hardware:

- epd_display_stream's 4KB SPI chunk buffer was a stack local, but the
  default main task stack (3584 bytes) is smaller than that alone --
  Guru Meditation stack protection fault. Made it static instead, and
  bumped CONFIG_ESP_MAIN_TASK_STACK_SIZE to 8192 for headroom in the rest
  of the boot call chain (provisioning -> QR render -> eventually the
  HTTP fetch cycle all run in this one task).

- epd_wait_busy() polled with a 1ms vTaskDelay, which rounds down to 0
  FreeRTOS ticks at the default 100Hz tick rate -- so it never actually
  blocked, tight-spinning the CPU for the panel's real refresh time
  (15-30+s for a full-color pass) and starving the idle task long enough
  to trip the 5s task watchdog. Bumped to 20ms, safely >=1 tick regardless
  of tick rate.

Also updates the EPD pin defaults to the board's actual wiring
(CLK=20 MOSI=19 CS=18 DC=9 RST=10 BUSY=11), confirmed working on hardware.
2026-07-18 14:06:54 -04:00

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menu "E-Paper Display (epd7in3e) Configuration"
config EPD_PIN_CLK
int "SPI CLK (SCLK) GPIO"
default 20
help
Defaults match the wiring on the reference build: CLK=20,
MOSI(DIN)=19, CS=18, DC=9, RST=10, BUSY=11. Override to match
your own wiring if different.
Note: DC uses GPIO9, one of the ESP32-C6's strapping pins
(sampled at reset to help select boot mode). It's only sampled
during power-on/reset, so it's safe to drive as a normal output
once the app is running -- but if flashing/boot ever misbehaves,
check whether the EPD is pulling this line low during reset.
config EPD_PIN_MOSI
int "SPI MOSI (DIN) GPIO"
default 19
config EPD_PIN_CS
int "SPI CS GPIO"
default 18
config EPD_PIN_DC
int "Data/Command GPIO"
default 9
config EPD_PIN_RST
int "Reset GPIO"
default 10
config EPD_PIN_BUSY
int "Busy GPIO"
default 11
config EPD_SPI_CLOCK_HZ
int "SPI clock speed (Hz)"
default 4000000
help
The panel's SPI interface is rated well above this, but dupont
wires/breadboards are often unreliable much past a few MHz.
Raise this once the physical wiring is confirmed solid.
endmenu