tfaour
474b92a282
Server: Frame.panel_type (new column + migration) is auto-derived from the device's reported board (X-Frame-Board), never user-set -- the panel is a property of the hardware, not a picker in the UI. image_pipeline's packing/render pipeline is parameterized by panel geometry instead of hardcoded 800x480 globals, with the real confirmed 13.3in geometry (1600x1200) registered alongside the original 7.3in panel. Existing 7.3in frames are unaffected (column default + board mapping both resolve to the original panel). Board identifiers are also renamed (devkit/xiao -> devkit_esp32c6/ xiao_esp32c6, plus new "ee02") since the EE02 board also carries a XIAO module -- "xiao" alone stopped disambiguating hardware. The server keeps accepting the legacy bare names indefinitely for already-flashed devices. Firmware: scaffolds a third build target (ee02, ESP32-S3 -- a real chip-target change, not just a same-chip Kconfig variant like xiao) and a new epd13in3e driver component skeleton. The actual panel init/LUT/ refresh register sequence isn't ported from vendor demo code yet (none was available), so that component deliberately fails to compile (#error) rather than risk sending unverified register values to real hardware -- devkit/xiao are unaffected and build identically to before. CI's ee02 build step is continue-on-error for the same reason.
66 lines
2.1 KiB
Plaintext
66 lines
2.1 KiB
Plaintext
menu "E-Paper Display (epd13in3e) Configuration"
|
|
|
|
config EPD_PIN_CLK
|
|
int "SPI CLK (SCLK) GPIO"
|
|
default 7
|
|
help
|
|
Defaults sourced from a community-verified ESPHome
|
|
integration for this exact board
|
|
(github.com/rkaramandi/esphome-seeed-ee02) -- NOT an
|
|
official Waveshare/Seeed reference driver (see
|
|
firmware/components/epd13in3e/epd13in3e.c's top comment,
|
|
which is about the still-unknown panel init/LUT/refresh
|
|
register sequence, a separate and larger unknown than this
|
|
pinout). Override if your own board wiring differs.
|
|
|
|
config EPD_PIN_MOSI
|
|
int "SPI MOSI (DIN) GPIO"
|
|
default 9
|
|
|
|
config EPD_PIN_CS_MASTER
|
|
int "SPI CS (master half) GPIO"
|
|
default 44
|
|
help
|
|
Unlike epd7in3e's single-CS interface, this panel is driven
|
|
as two halves over one shared CLK/MOSI/DC/RST/BUSY bus with
|
|
two independent chip-selects (master/slave) -- confirmed by
|
|
the same community ESPHome integration, not yet by this
|
|
component's own driver code (still unimplemented, see
|
|
epd13in3e.c).
|
|
|
|
config EPD_PIN_CS_SLAVE
|
|
int "SPI CS (slave half) GPIO"
|
|
default 41
|
|
|
|
config EPD_PIN_DC
|
|
int "Data/Command GPIO"
|
|
default 10
|
|
|
|
config EPD_PIN_RST
|
|
int "Reset GPIO"
|
|
default 38
|
|
|
|
config EPD_PIN_BUSY
|
|
int "Busy GPIO"
|
|
default 4
|
|
|
|
config EPD_PIN_POWER_EN
|
|
int "Panel power-enable GPIO"
|
|
default 43
|
|
help
|
|
No equivalent pin on epd7in3e's board -- the EE02 apparently
|
|
gates the panel's own power rail separately from the ESP32-S3
|
|
module's. Source: same community integration as the other
|
|
pins above.
|
|
|
|
config EPD_SPI_CLOCK_HZ
|
|
int "SPI clock speed (Hz)"
|
|
default 2000000
|
|
help
|
|
2MHz, not epd7in3e's 4MHz default -- the same community
|
|
integration notes higher rates were unreliable on this
|
|
panel/board combo. Revisit once wiring is confirmed on real
|
|
hardware.
|
|
|
|
endmenu
|